Power reduction using high speed with saving mode clock gating technique
نویسندگان
چکیده
منابع مشابه
Power reduction on clock-tree using Energy recovery and clock gating technique
Power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. Th...
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ژورنال
عنوان ژورنال: IOP Conference Series: Materials Science and Engineering
سال: 2021
ISSN: 1757-8981,1757-899X
DOI: 10.1088/1757-899x/1076/1/012055